library ieee;
use ieee.std_logic_1164.all;
use work.fir_pack.all;
use work.components_pack.all;

entity fir_top is
  
  port (
    clk, rst  : in  std_logic;
    fir_in    : in std_logic_vector(INPUT_WIDTH-1 downto 0);
    fir_out   : out std_logic_vector(INPUT_WIDTH+COEFF_WIDTH+M-1 downto 0)
);

end fir_top;

architecture structural of FIR_top is

component fir
     port (
      clk, rst : in  std_logic;
      x        : in  std_logic_vector(INPUT_WIDTH-1 downto 0);
      y        : out std_logic_vector(OUTPUT_WIDTH-1 downto 0));
end component;

----------------------------------------------------------------------------

-- signal definitions here if needed
   signal fir_i:            std_logic_vector(INPUT_WIDTH-1 downto 0);
   signal fir_o:            std_logic_vector(OUTPUT_WIDTH-1 downto 0);

begin
-- Input Register
  
                dff_input:  dff
                    generic map (
                          w => INPUT_WIDTH )
                    port map (
                       clk => clk,
                       rst => rst,
                       d   => fir_in,
                       q   => fir_i
                       );
  
  -- Output Register
  
                dff_output:  dff
                    generic map (
                          w => OUTPUT_WIDTH )
                    port map (
                       clk => clk,
                       rst => rst,
                       d   => fir_o,
                       q   => fir_out
                       );
 
FIR1 : fir
  port map (
    clk => clk,
	 rst => rst,
	 x => fir_i,
    y => fir_o
	 );
 

end structural;
